June 2011 Vol. 2, Iss. 42

Dear Subscriber: 

When BGA interconnection problems come up, do not forget that BEST can help you diagnose and troubleshoot these problems. Dye and pry services from BEST can help pinpoint wettability, pad cratering and cracked laminate problems.

My son, his friend and the friend's father and I had a fun time at a local night mud run. Military personnel barked at us at the (7) obstacles over the 5K course as we climbed over rope ladders, shimmied through a mud pit and climbed up an incline. Big fun!

(Mud run final 50 yards-belly crawling through mud)

As a reminder do not forget to see us at the following upcoming regional exhibits:

Wednesday June 22nd Huntsville
Thursday July 14th Cleveland 

We invite you to our leadless device, reballing and advanced package rework seminar as part of the IPC Midwest, September 21st:

IPC Midwest Invite Advanced Package Rework

Bob Wettermann
President, BEST Inc

PS- See our fun new "About BEST" page.

If you are having process problems with BGAs, CSPs or leadless devices, dye and pry analysis is a first level troubleshooting methodology for determining an interconnection problem. Problems such as contaminated pads, cracked laminate or a cracked device solder joint can be discovered through the use of this destructive test. Dye is squirted underneath the package and after breaking the device from the board the analysis can show where the penetrant "leaked" in to.  

A sample report can be found here.

Call Laura Ripoli at (847) 797-9250 to discuss your project. 

BEST Partners with RCBI

Mid Atlantic Professional Solder Training 

Our schedule for this and other classes for the 2nd half of 2011 can now be found on our web site.

Call Katy at BEST at (847) 797-9250 for more information. 

3D Transistor-Moving Down the Moore Curve

For the first time since the invention of silicon transistors more than 50 years ago, transistors using a three-dimensional structure will be put into high-volume manufacturing. To do so, Intel will deploy a 3D transistor design (codenamed 'Ivy Bridge') called Tri-Gate into high-volume manufacturing.

The traditional 'flat' two-dimensional planar gate has been replaced with a thin three-dimensional silicon fin that rises up vertically from the silicon substrate. Control of the current through the transistor is accomplished by implementing a gate on each of the three sides of the fin - two on each side and one across the top - rather than just one on top, as is the case with a 2D planar transistor.

The additional control enables as much transistor current flowing as possible when the transistor is in the 'on' state and as close to zero as possible when it is in the 'off' state, and enables the transistor to switch quickly between the two states.

The new transistors consume less than half the power when at the same performance as 2D planar transistors on 32nm chips.